Regulator and semiconductor device

ABSTRACT

A regulator including a differential amplifier including a differential input stage that differentially receives a reference voltage and an output terminal voltage of the regulator, a drive transistor that has an output connected to an output terminal of the regulator and that has a control terminal connected to an output of the differential amplifier, a first transistor connected between the control terminal of the drive transistor and a first power supply terminal and a second transistor connected between the control terminal of the drive transistor and a second power supply terminal, wherein a control terminal of the first transistor and a control terminal of the second transistor are connected to a first control signal and a second control signal, respectively, the first transistor being on-off controlled by the first control signal and the second transistor being on-off controlled by the second control signal.

The present application is a Continuation Application of U.S. patentapplication Ser. No. 12/458,623, filed on Jul. 17, 2009, which is basedon and claims the benefit of priority of Japanese patent application No.2008-187084, filed on Jul. 18, 2008, the entire contents of which isincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a regulator for generating an internalvoltage of a semiconductor device from a power supply voltage.

BACKGROUND

In Patent Document 1, there is disclosed a voltage conversion circuit(regulator) including a differential amplifier with a push-pull outputstructure of a current mirror configuration. In order to describe thevoltage conversion circuit in Patent Document 1, FIG. 10 is createdbased on FIG. 1 of Patent Document 1. Referring to FIG. 10, the voltageconversion circuit includes an error amplifier that is configured as adifferential amplifier and that outputs error amplification output to anode N1, and a buffer circuit that receives the output from the erroramplifier and outputs an output voltage Vout3 to a node N2. Thedifferential amplifier as the error amplifier includes a differentialinput stage and a push-pull type output unit of a current mirror circuitconfiguration.

In more detail, referring to FIG. 10, the differential input stage ofthe differential amplifier includes:

an n-channel MOS transistor (current source transistor) Q9 that has asource connected to GND (ground) and has a gate to which a bias voltageBN I supplied;

a differential pair including:

n-channel MOS transistors Q1 and Q2 that have sources coupled togetherand connected to a drain of the current source transistor Q9; and

diode-connected p-channel MOS transistors Q3 and Q5 that have sourcesconnected in common to a power supply terminal VDD, and have drainsrespectively connected to drains of the transistors Q1 and Q2.

The differential amplifier output portion (push-pull type output portionof the current mirror circuit configuration) includes:

a p-channel MOS transistor Q4 that has a source connected to the powersupply terminal VDD and has a gate connected to a gate of the p-channelMOS transistor Q3;

a p-channel MOS transistor Q6 that has a source connected to the powersupply terminal VDD and has a gate connected to a gate of the p-channelMOS transistor Q5;

an n-channel MOS transistor Q7 that has a source connected to ground andhas a drain and a gate connected to a drain of the p-channel MOStransistor Q4; and

an n-channel MOS transistor Q8 that has a source connected to GND, has agate connected to a gate of the n-channel MOS transistor Q7, and has adrain connected to a drain of the transistor Q6. The transistors Q8 andQ6 compose push-pull transistors. The p-channel MOS transistors Q3 andQ4 compose a first current mirror circuit, the p-channel MOS transistorsQ5 and Q6 compose a second current mirror circuit, and the n-channel MOStransistors Q7 and Q8 form a compose third current mirror circuit.

A reference voltage Vref is supplied from a reference voltage generationcircuit (not shown), to the gate of the n-channel MOS transistor Q1constituting the differential pair, and an output Vout3 of the buffercircuit is fed back to a gate of the n-channel MOS transistor Q2. Thebias voltage BN (denoted as F1 in Patent Document 1) is supplied from abias circuit (not shown) to a gate of the current source transistor Q9.

The buffer circuit includes:

a p-channel MOS transistor (drive transistor) Q10 that has a sourceconnected to a power supply terminal VDD, has a gate connected to a nodeN1 (output of differential amplifier output portion), and has a drainconnected to a node N2 (regulator output); and

a resistance element R1 between the node N2 and GND. Patent Document 1,the resistance element R1 between the node N2 and GND includes ann-channel MOS transistor (not shown in FIG. 10) that has a sourceconnected to GND, has a drain connected to the node N2, and has a gateto which a bias voltage is supplied. This n-channel MOS transistor isarranged such that a current source is configured so that a current(idling current) of an appropriate amount flows in the drive transistorQ10 even when a load current I3 becomes particularly small.

The drive transistor Q10 is in an operation state so as to have anappropriate gain, irrespective of large amount of change in the loadcurrent I3 due to this idling current. In Patent Document 1, there isprovided a p-channel MOS transistor (control transistor) (not shown inFIG. 10) that has a source connected to the power supply terminal VDD,has a gate connected to a bias voltage, and has a drain connected to thenode N1. This control transistor is provided so that, byswitch-controlling the gate bias voltage BN (F1 in Patent Document 1) ofthe current source transistor Q9 to 0V, when operation of the voltageconversion circuit is stopped, synchronization thereto is performed, andthe drive transistor Q10 is preferably cut off.

In the configuration of FIG. 10, the amount of current flowing to thepush-pull type output portion transistors Q6 and Q8, is adjusted by thedifferential input stage and the current mirror circuit and the gatepotential of the drive transistor Q10 is able to be lowered to almost aGND potential. It is possible to increase gate-to-source voltage of thedrive transistor Q10, and to increase drive capability of the buffercircuit (drive transistor Q10).

Patent Document 1

-   JP Patent Kokai Publication No. JP-A-10-64261

SUMMARY

The entire disclosure of Patent Document 1 is incorporated herein byreference thereto.

An analysis of the related art according to the present invention isgiven as follows.

In recent years with regard to large capacity memory and so forth, anoutput load current of a regulator tends to increase in order to achievehigh speed access. In particular, response speed of the regulator to atransient increase in the load current immediately after memory accessis important.

When the response speed of the regulator is not sufficient, there is aconcern regarding the occurrence of:

output potential drop immediately after memory access;

erroneous judgment due to over precharging after memory access;

operation margin decrease; and

overstress.

Therefore, it is important to increase drive capability of a drivetransistor of a regulator in lowering the power supply voltage and ahigher response speed of the regulator is also required.

In the configuration described with reference to FIG. 10, when theresponse speed of the regulator is raised against the transient increasein the load current immediately after memory access, current consumptionincreases. This point will be described below.

In FIG. 10, a current flowing in a path of the transistors Q6 and Q8 ofthe push-pull type output portion of the differential amplifier isdetermined by a current flowing in the current source transistor Q9, ora mirror ratio (ratio of transistor dimensions) of a current mirrorcircuit. In the differential amplifier, a current flowing in the currentsource transistor Q9 is constant (constant current). With regard to theresponse speed of the regulator against a transient increase in loadcurrent immediately after memory access, adjustment is necessary byincreasing operation current (that is, current of the current sourcetransistor Q9) of the regulator so that current consumption increases.

For example, in increasing output current (drain current) of the drivetransistor Q10 for a transient increase in the load current I3, it isnecessary to pull down a gate potential of the drive transistor Q10 to aGND potential. Here, in discharging the gate of the drive transistor Q10in order to pull down the gate potential to the GND potential at highspeed, it is necessary to increase a drain current of the n-channel MOStransistor Q8 of the push-pull type output portion. The drain current ofthe n-channel MOS transistor Q8 is a mirror current of the a draincurrent of the n-channel MOS transistor Q7, and the drain current of then-channel MOS transistor Q7 is equal to a drain current of the p-channelMOS transistor Q4 (which is a mirror current of a drain current of thep-channel MOS transistor Q3. In order to discharge the gate node N1 ofthe drive transistor Q10 at high speed, it is necessary to increase thecurrent value of the current source transistor Q9. This increasescurrent consumption.

Accordingly, it is an object of the present invention to provide aregulator that enables a high speed response and enables to keep anoutput stable, against a transient increase in an output load current,without increasing current consumption.

In order to solve one or more of the abovementioned problems, thepresent invention disclosed herein is configured in outline as follows.

According to a first aspect of the present invention, there is provideda regulator including: a differential amplifier including a differentialinput stage that differentially receives a reference voltage and anoutput terminal voltage of the regulator; a drive transistor that has anoutput connected to an output terminal of the regulator and that has acontrol terminal connected to an output of the differential amplifier;first and second transistors connected in series between the controlterminal of the drive transistor and a first power supply terminal; andthird and fourth transistors connected in series between the controlterminal of the drive transistor and a second power supply terminal. Acontrol terminal of the first transistor and a control terminal of thethird transistor are directly or indirectly connected to outputs of thedifferential input stage and a control terminal of the second transistorand a control terminal of the fourth transistor are connected to a firstcontrol signal and a second control signal, respectively. The secondtransistor is on-off controlled by the first control signal and thefourth transistor is on-off controlled by the second transistor. In thepresent invention, a control terminal voltage of the drive transistor iscontrolled, based on the first and the second control signals, by outputof the differential amplifier, or by output of the differentialamplifier and the first transistor, or by output of the differentialamplifier and the third transistor.

According to the present invention, it is possible to speed up aresponse and to maintain a stable output voltage, against a transientincrease in an output load current, without increasing currentconsumption.

Still other features and advantages of the present invention will becomereadily apparent to those skilled in this art from the followingdetailed description in conjunction with the accompanying drawingswherein only exemplary embodiments of the invention are shown anddescribed, simply by way of illustration of the best mode contemplatedof carrying out this invention. As will be realized, the invention iscapable of other and different embodiments, and its several details arecapable of modifications in various obvious respects, all withoutdeparting from the invention. Accordingly, the drawing and descriptionare to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a first exemplaryembodiment of a regulator of the present invention.

FIG. 2 is a timing waveform diagram describing operation of the firstexemplary embodiment of the regulator of the present invention.

FIG. 3 is a diagram showing a configuration of a second exemplaryembodiment of a regulator of the present invention.

FIG. 4 is a diagram schematically showing a configuration of asemiconductor integrated circuit device provided with the regulator ofthe present invention.

FIG. 5 is a diagram showing one example of a configuration of a memoryblock part of FIG. 4.

FIG. 6 is a timing waveform diagram for describing operation of FIG. 5.

FIG. 7 is a timing waveform diagram describing operation of an exemplaryembodiment of the present invention.

FIG. 8 is a diagram showing another configuration example of the memoryblock part of FIG. 4.

FIG. 9 is a timing waveform diagram describing operation of an exemplaryembodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a regulator of relatedart.

PREFERRED MODES OF THE INVENTION

In accordance with the present invention, a regulator includes:

a differential amplifier having differential inputs connected to areference voltage (Vref) and an output terminal voltage (Vout1);

a drive transistor (Q10) that has an output connected to an outputterminal of a regulator and has a control terminal (N1) connected to anoutput of the differential amplifier and that has an output currentcontrolled by a voltage at the control terminal (N1);

first and second transistors (Q11 and Q12) cascode-connected between thecontrol terminal (N1) of the drive transistor (Q10) and a first powersupply terminal (GND); and

third and fourth transistors (Q13 and Q14) cascode-connected between thecontrol terminal (N1) of the drive transistor (Q10) and a second powersupply terminal (VDD).

The differential amplifier has a differential input stage including:

a current source Q9;

a differential pair (Q1 and Q2), and

loads (Q3 and Q5).

The differential amplifier includes the differential input stage and adifferential amplifier output portion with a push-pull output structureof a current mirror configuration (Q4, Q7, Q8, and Q6).

The control terminal of the first transistor (Q11) is indirectly (forexample, indirectly via the transistors Q3, Q4, Q7, and Q8) connected toan output of the differential input stage (an output of the differentialpair transistor (Q1)).

The control terminal of the third transistor (Q13) is directly connectedto an output of the differential input stage (the output of thedifferential pair transistor (Q2)).

The control terminals of the second and fourth transistors (Q12 and Q14)are respectively connected to first and second control signals (IN1 andIN2).

When the control terminal voltage of the drive transistor (Q10) ischanged to the first power supply voltage (GND), the first controlsignal (IN1) is activated to turn on the second transistor (Q12), andthe control terminal voltage of the drive transistor (Q10) is changed tothe first power supply voltage (GND) side, by the output of thedifferential amplifier (an output of the transistor Q8) and the firsttransistor (Q11). When the control terminal voltage of the drivetransistor (Q10) is changed to the second power supply voltage (VDD),the second control signal (IN2) is activated to turn on the fourthtransistor (Q14), and the control terminal voltage of the drivetransistor (Q10) is changed to the second power supply voltage (VDD)side, by the output of the differential amplifier (an output of thetransistor Q6) and the third transistor (Q13). A description will begiven below according to exemplary embodiments.

FIG. 1 is a diagram showing a configuration of a regulator of a firstexemplary embodiment of the present invention. In the present exemplaryembodiment, the regulator includes a differential amplifier as an erroramplifier, similar to FIG. 10, and a buffer circuit. The differentialamplifier includes a differential input stage, and a push-pull typeoutput portion of a current mirror configuration.

In FIG. 1, the differential input stage of the differential amplifierincludes:

an n-channel MOS transistor (current source transistor) Q9 that has asource connected to GND, and has a gate to which a bias voltage BN issupplied;

a differential pair including n-channel MOS transistors Q1 and Q2 thathave sources coupled and connected to a drain of the current sourcetransistor Q9; and

diode-connected p-channel MOS transistors Q3 and Q5 that have sourcesare connected in common to a power supply terminal VDD, and have drainsrespectively connected to drains of the transistors Q1 and Q2.

The differential amplifier output portion (push-pull type output portionof the current mirror circuit configuration) includes:

a p-channel MOS transistor Q4 that has a source connected to the powersupply terminal VDD and has a gate connected to a gate of the p-channelMOS transistor Q3;

a p-channel MOS transistor Q6 that has a source connected to the powersupply terminal VDD and has a gate connected to a gate of the p-channelMOS transistor Q5;

an n-channel MOS transistor Q7 that has a source connected to GND andhas a drain and a gate connected to a drain of the p-channel MOStransistor Q4; and

an n-channel MOS transistor. Q8 that has a source connected to GND, hasa gate connected to a gate of the n-channel MOS transistor Q7, and has adrain connected to a drain of the transistor Q6. The transistors Q8 andQ6 compose push-pull transistors. The p-channel MOS transistors Q3 andQ4 compose first current mirror circuit, the p-channel MOS transistorsQ5 and Q6 compose a second current mirror circuit, and the n-channel MOStransistors Q7 and Q8 compose a third current mirror circuit.

A reference voltage Vref is supplied from a reference voltage generationcircuit (not shown), to the gate of the n-channel MOS transistor Q1,constituting the differential pair, and a regulator output Vout1 is fedback to a gate of the n-channel MOS transistor Q2.

The bias voltage BN is supplied from a bias circuit (not shown) to agate of the current source transistor Q9.

The buffer circuit includes:

a p-channel MOS transistor (drive transistor) Q10 that has a sourceconnected to the power supply terminal VDD, has a gate connected to anode N1 (output of differential amplifier output portion), and has adrain connected to a node N2 (output of regulator); and

a resistance element R1 between the node N2 and GND.

In FIG. 1, the abovementioned current source transistor Q9, then-channel MOS transistors (differential pair) Q1 and Q2, the p-channelMOS transistors (load circuits) Q3 and Q5, the p-channel MOS transistorQ4 composing a first current mirror circuit with the p-channel MOStransistor Q3, the p-channel MOS transistor Q6 composing a secondcurrent mirror circuit with the p-channel MOS transistor Q5, then-channel MOS transistors Q7 and Q8 composing a third current mirrorcircuit, and the drive transistor Q10 that composes the buffer circuitare basically the same, respectively, as the transistors of the samereference symbols in FIG. 10.

Referring to FIG. 1, in the regulator of the present exemplaryembodiment, n-channel MOS transistors Q11 and Q12, and p-channel MOStransistors Q13 and Q14 are added as compare with the configuration ofFIG. 10.

The n-channel MOS transistor Q11 has a drain connected to the node N1,and has a gate connected to a common connection node of the drain andthe gate of the n-channel MOS transistor Q7, and the gate of then-channel MOS transistor Q8.

The n-channel MOS transistor Q12 has a source connected to a GNDterminal, and has a gate supplied with a first driver control signalIN1, and has a drain connected to a source of the n-channel MOStransistor Q11.

The p-channel MOS transistor Q13 has a drain connected to the node N1,and has a gate thereof connected to a common connection node of thedrain and the gate of the p-channel MOS transistor Q5, and the gate ofthe p-channel MOS transistor Q6. That is, the gate of the p-channel MOStransistor Q13 is directly connected to one differential output of thedifferential input stage (a drain of the transistor Q5). The gate of then-channel MOS transistor Q11 is indirectly connected, via the currentmirror circuits (Q3, Q4, Q7, and Q8) to the other differential output ofthe differential input stage (a drain of the transistor Q3).

The p-channel MOS transistor Q14 has a source connected to the powersupply terminal VDD, has a gate thereof connected to a second drivercontrol signal IN2, and has a drain connected to a source of thep-channel MOS transistor Q13.

The n-channel MOS transistors Q11 and Q12, which are cascode-connectedbetween the node N1 and a GND terminal, operate so as to equivalentlyincrease the size (drive capability) of the n-channel MOS transistor Q8of the differential amplifier output portion, which shifts the potentialof the node N1 to a GND side.

The p-channel MOS transistors Q13 and Q14, which are cascode-connectedbetween the power supply terminal VDD and the node N1, operate so as toequivalently increase the size (drive capability) of the p-channel MOStransistor Q6 of the differential amplifier output portion, which shiftsthe potential of the node N1 to a power supply voltage VDD side.

The first and second driver control signals IN1 and IN2 respectivelycontrol the n-channel MOS transistor Q12 and the p-channel MOStransistor Q14, and serves to changes over the size of the transistorsQ8 and Q6 that form the differential amplifier output portion.

FIG. 2 is a waveform diagram for illustrating operation of FIG. 1. InFIG. 2, a current waveform (transient change) of a load current I1 ofFIG. 1, a voltage waveform of the first and second driver controlsignals IN1 and IN2, and a waveform of the output voltage Vout1 of theregulator are shown.

Referring to FIG. 2, when the load current I1 is not flowing (defaultsituation), both the first and the second driver control signals IN1 andIN2 are inactive (IN1 is Low, and IN2 is High), and both the transistorsQ12 and Q14 in FIG. 1 are set to an off state. Therefore, thetransistors Q11 and Q13 are in an off state. At this time, the potentialof the gate node N1 of the drive transistor Q10 is controlled based onoutput (Q6 and Q8) of the output portion of the differential amplifier.

When the load is operated and the load current I1 flows, the outpourvoltage Vout1 of the regulator drops. At this time, to promptly restorethe output potential Vout1 to an expected value, it is necessary toshift the potential of the gate node N1 of the drive transistor Q10 tothe GND potential side, and to promptly increase current supplycapability of the regulator.

In the present exemplary embodiment, with the first driver controlsignal IN1 High, the n-channel MOS transistor Q12 is turned on, the sizeof the output portion of the differential amplifier is increased fromthe n-channel MOS transistor Q8 to a total of the n-channel MOStransistors Q8 and Q11, the current drive capability is raised, and thenode N1 is shifted to the GND potential side. In this way, the currentsupply capability of the buffer circuit (drive transistor Q10) of theregulator is promptly increased. At this time, since the second drivercontrol signal IN2 is High, and the p-channel MOS transistor Q14 is inan off state, there is no current supply (charging) from the p-channelMOS transistor Q13 to the node N1.

Although there is no particular limitation, when the load current I1decreases, the first driver control signal IN1 is set to Low and then-channel MOS transistor Q12 is turned off. The node N1 is discharged toGND potential by only the n-channel MOS transistor Q8. As a result,slew-rate of falling of the node N1 to the GND potential is lowered. Theslew-rate of rising of the output voltage Vout1 of the regulator to thepower supply potential VDD side also is lowered.

In FIG. 2, an output voltage waveform indicated by “related art” is anoutput voltage waveform of the regulator of FIG. 10.

From FIG. 2, it is understood that a response characteristic of theoutput voltage Vout1 (indicated by the exemplary embodiment) of theregulator of the present exemplary embodiment surpasses a responsecharacteristic of the related art.

If the n-channel MOS transistor Q12 is removed and there is only then-channel MOS transistor Q11 that has a gate connected with a gate ofthe n-channel MOS transistor Q8 between the node N11 and GND, the nodeN1 is discharged by the n-channel MOS transistors Q8 and Q11 and pullingdown of the node N1 to a GND potential is fastened. However, there arecases where over-drive occurs due to excess current supply from thedrive transistor Q10 to the load. In such cases, it takes more time forthe output voltage to become stable.

In the present exemplary embodiment, the n-channel MOS transistor Q11that has a gate connected with a gate of the n-channel MOS transistorQ8, and the n-channel MOS transistor Q12 that has a gate supplied withthe first driver control signal IN1, are cascode-connected. Then-channel MOS transistor Q12 operates to limit sink current from thenode N1 by the n-channel MOS transistor Q11. As a result, the occurrenceof over-drive due to excess current supply to the load by the drivetransistor Q10 is suppressed.

If the load current I1 ceases to flow, it is necessary to shift the nodeN1 to the power supply potential VDD in order to promptly transitionsupply capability of the regulator to an equilibrium state.Consequently, in the present exemplary embodiment, the second drivercontrol signal IN2 is set to Low, the p-channel MOS transistor Q14 isturned on, the transistor size of the output portion of the differentialamplifier is increased from the p-channel MOS transistor Q6 to a totalof the p-channel MOS transistors Q6 and Q13, and the node N1 transitionseasily to the power supply potential VDD side. When the second drivercontrol signal IN2 is Low and the node N1 shifts to the power supplypotential VDD side, the current supply to the load of the drivetransistor Q10 decreases, and the output voltage Vout1 is loweredtowards the reference voltage Vref.

When the second driver control signal IN2 is Low, since the first drivercontrol signal IN1 is Low and the n-channel MOS transistor Q12 is turnedoff, there is no current dissipation from the n-channel MOS transistorQ11.

If the p-channel MOS transistor Q14 is removed, and there is only thep-channel MOS transistor Q13 that has a gate connected to a gate of thep-channel MOS transistor Q, the pulling up of the node N1 to the powersupply potential VDD side is fastened, and current supply from the drivetransistor Q10 to the load becomes too small. As a result, outputvoltage drops more than necessary, and time until the output voltagebecomes stabile is elongated.

In the present exemplary embodiment, the p-channel MOS transistor Q13that has a gate connected to a gate of the p-channel MOS transistor Q6,and the p-channel MOS transistor Q14 that has a gate supplied with thesecond driver control signal IN2, are cascode-connected between the nodeN1 and the power supply terminal VDD. The p-channel MOS transistor Q14limits current supply to the node N1 from the p-channel MOS transistorQ13. As a result, the current supply from the drive transistor Q10becomes too small, and the occurrence of a state in which the outputvoltage Vout1 drops is suppressed.

In FIG. 2, the second driver control signal IN2 may be set to a Lowlevel at timing indicated by a broken line earlier than timing indicatedby the solid line and may. When the first driver control signal IN1 goesfrom High to Low, the n-channel MOS transistor Q12 turns off, and acharge of the node N1 is discharged to a GND potential by only then-channel MOS transistor Q8. When the second driver control signal IN2is set to a Low level at a timing indicated by the broken line, thep-channel MOS transistor Q14 turns on, and according to a differencepotential between the output voltage Vout1 and the reference voltageVref, the node N1 is discharged by the n-channel MOS transistor Q8 andalso is charged by the p-channel MOS transistor Q13. The slew-rate offalling of the node N1 to the GND potential is lowered. As a result, theslew-rate of rising of the output voltage Vout1 of the regulator to thepower supply potential VDD is also reduced. However, in this case, theresponse characteristic of the output voltage of the regulator to theincrease in load current is at a higher speed than the related art.

The resistance element R1 between the node N2 and GND may be replaced bya current source transistor. That is, a replacement may be made with ann-channel MOS transistor that has a source connected to GND, has a drainconnected to the node N2, and has a gate connected to a bias voltageterminal. This n-channel MOS transistor composes a current source inorder that a current (idling current) of an appropriate amount flows inthe drive transistor Q10 even when the load current I1 becomesparticularly small. Such a configuration is also possible in which thata p-channel MOS transistor (control transistor) that has a sourceconnected to the power supply terminal VDD, has a gate connected to abias voltage terminal, and has a drain connected to the node N1. Thiscontrol transistor performs switching control of the gate bias voltageBN of the current source transistor Q9 to 0V, for example, whenoperation of the regulator is stopped, in synchronization therewith tocut off the drive transistor Q10.

FIG. 3 is a diagram showing a configuration of a regulator of a secondexemplary embodiment of the present invention. In the present exemplaryembodiment, a differential amplifier of the above-mentioned firstexemplary embodiment, which has a differential input stage and push-pulltype output portion of a current mirror configuration, shown in FIG. 1,is substituted for a configuration in which only the differential inputstage is provided.

Referring to FIG. 3, in the present exemplary embodiment, thedifferential amplifier includes:

a current source transistor Q9 that has a source connected to GND andhas a gate to which a bias voltage BN is supplied;

a differential pair including n-channel MOS transistors Q1 and Q2, thathave sources coupled together and connected to a drain of the currentsource transistor Q9, and have gates to which a reference voltage Vrefand an output voltage Vout2 are supplied respectively;

a p-channel MOS transistor Q3 that has a source connected to a powersupply terminal VDD, and has a drain connected to a drain of thetransistor Q1; and

a p-channel MOS transistor Q5 that has a source connected to the powersupply terminal VDD, has a gate and a drain coupled together andconnected to a gate of the transistor Q3 and also connected to a drainof the transistor Q2.

A p-channel MOS transistor (drive transistor) Q10 that has a sourceconnected to the power supply terminal VDD and has a drain connected tothe node N2 and has a gate connected to a connection node (one ofdifferential outputs of the differential input stage) of a drain of then-channel MOS transistor Q1 constituting a differential pair, and adrain of the p-channel MOS transistor Q3 constituting a load element.

The regulator according to the present exemplary embodiment includes:

p-channel MOS transistors Q13 and Q14 that are cascode-connected betweenthe power supply terminal VDD and a gate node N1 of the drive transistorQ10, and

n-channel MOS transistors Q12 and Q11 that are cascode-connected betweenGND and the gate node N1 of the drive transistor Q10. A first drivercontrol signal IN1 is supplied to a gate of the n-channel MOS transistorQ12. A second driver control signal IN2 is supplied to a gate of thep-channel MOS transistor Q14.

The n-channel MOS transistor Q11 and the p-channel MOS transistor Q13have gates connected in common to the drain of the n-channel MOStransistor Q2 constituting the differential pair, and a node N3 (theother of the differential outputs of the differential input stage),which is a connection node of the drain and gate of the p-channel MOStransistor Q5 constituting the load element.

In the present exemplary embodiment, in a default situation, the firstand second driver control signals IN1 and IN2 are both set to beinactive, and the transistors Q12 and Q14 are turned off. A potential ofthe gate node N1 of the drive transistor Q10 is controlled by output ofthe differential amplifier (output of the transistor Q1).

When a load current I2 flows, and an output potential Vout2 drops, inorder to restore the output voltage Vout2 promptly to an expected value,it is necessary to shift the gate node N1 of the drive transistor Q10 toa GND potential, and to promptly increase current supply capability ofthe regulator.

By activating the first driver control signal IN1, the size of then-channel MOS transistor Q1 constituting the differential pair, isequivalently enlarged to the n-channel MOS transistor Q1 plus Q11, thenode N1 is transitioned easily to a GND potential side, and the currentsupply capability from the regulator is promptly increased. At thistime, the p-channel MOS transistor Q13 is turned off, and there is nocurrent supply from the p-channel MOS transistor Q13 to the node N1.That is, since each path of the n-channel MOS transistor Q11 and thep-channel MOS transistor Q13 are not on at the same time, there is noincrease in current dissipation of the regulator.

When the load current I2 ceases to flow, in order to promptly transitionthe current supply capability of the regulator to an equilibrium state,it is necessary to shift the node N1 to the power supply potential VDDside. At this time, in the present exemplary embodiment, the p-channelMOS transistor Q14 is turned on by the second driver control signal IN2,and hence the total driver size of the output portion of thedifferential amplifier is increased from the p-channel MOS transistor Q3to that of the p-channel MOS transistors Q3 plus Q13. As a result, thenode N1 transitions easily to the power supply potential VDD side.

As described above, in the regulator of the above-mentioned presentexemplary embodiment, the transistors Q11, Q12, Q13, and Q14, whichequivalently change transistor size of the differential pair thatcontrols a gate potential of the drive transistor Q10, based on acontrol signal, are provided. The speed up of a response of theregulator to the change of the regulator output load current is achievedand change in regulator output voltage is suppressed. In this way,variations in circuit operation are decreased and high speed operationis made possible.

Next, a semiconductor device including a regulator of the abovedescribed present invention will be described. FIG. 4 is a diagramshowing a configuration of a semiconductor integrated circuit deviceincluding the regulator of the present exemplary embodiment. Referringto FIG. 4, the semiconductor integrated circuit device 1 includes aregulator unit (REG1 and REG2) 10, a memory block 20, a peripheralcircuit 30, and an input/output interface 40. The regulator unit (REG1and REG2) 10 includes a plurality of regulators described with referenceto FIG. 1 to FIG. 3, receive the reference voltage Vref, and generateinternal power supplies (VREG1 and VREG2) from the power supply voltageVDD. Although there is no particular limitation, in the example shown inFIG. 4, an internal power supply (VREG1) from the regulator (REG1) issupplied to the memory block 20, and an internal power supply (VREG2)from the regulator (REG2) is supplied to the peripheral circuit 30. Theinternal power supplies (VREG1 and VREG2) are at a stable level,independent of variations of the power supply voltage VDD. It should benoted that the number of regulators in the regulator unit (REG1 andREG2) is not limited to 2.

The memory block 20 includes a memory array, a decoder circuit, a senseamplifier, and a timing circuit (none of which are shown), and performsa circuit operation with the internal power supply VREG1 as a powersupply.

The peripheral circuit 30 includes a control circuit that controlstransfer of address and data signals between the memory array and asignal that is externally supplied to a chip, via the input/outputinterface 40, and various types of mode entry control circuits, and atiming circuit (none of which are shown), and performs a circuitoperation with the internal power supply VREG2 as a power supply. Theperipheral circuit part 30 supplies address information, memory celldata, and a sense amplifier activation signal to the memory block 20.

The input/output interface 40 is disposed between the signal externallysupplied to the chip and the peripheral circuit 30, and includes buffersfor address, data, and various command signals, and a level conversioncircuit (none of which are shown). Although there is no particularlimitation imposed on the control signals, in the example of FIG. 1, ascontrol signals, a chip select signal CE, an output enable signal OE,and an address signal ADD are received, and data DATA is received andoutput.

FIG. 5 is a diagram showing a configuration of the memory block 20 ofFIG. 4. Referring to FIG. 5, the memory block 20 includes a memory cell(although there is no limitation imposed on the memory cell, in thisexample, the memory cell may be an EEPROM (Electrically ErasableProgrammable Read Only Memory) cell, such as Flash Memory, or the like),a timing circuit 21, a decoder circuit 22, and a sense amplifier 25. InFIG. 5, only for simplicity's sake, one cell (C1) that is selected(termed select cell) is shown as the memory cell, and a reference cell(dummy cell) C2, which gives a bit line reference voltage, is shown.

The decoder circuit 22 decodes the address information to select thememory cell by a generated signal. In FIG. 5, the decoder circuit 22includes an X decoder (not shown) that decodes an X address (rowaddress) of the address information and selects a word line WL, and a Ydecoder (not shown) that decodes a Y address (column address) of theaddress information and outputs a Y selector (column select signal) thatselects a Y switch (column switch).

A bit line BL1 selected by a Y switch (Y1, Y2), out of bit lines of thememory array, and a bit line BL2 that is a reference, are connected tothe sense amplifier 25. In FIG. 2, only for simplicity's sake, amongplural bit lines of the memory array, only a bit line connected to theselect cell C1 and a bit line connected to the reference cell C2 areshown.

The timing circuit 21 generates a precharge signal PRE, a sensing signal(sense enable signal) SEN, and a sense latch signal LAT, from the senseamplifier activation signal received from the peripheral circuit 30 tosupply the so generated signal to a bit line BL precharge circuit andthe sense amplifier 25.

The bit line BL precharge circuit includes: an n-channel MOS transistorM1 that is connected between a precharge power supply terminal and a bitline BL1 and that has a gate to which the precharge signal PRE issupplied; and an n-channel MOS transistor M2 that is connected betweenthe precharge power supply terminal and the bit line BL2, and that has agate to which the precharge signal PRE is supplied.

The sense amplifier 25 includes: switches (pass transistors) S1 and S2that have gates to which a sensing signal (sense enable signal) SEN issupplied and that connect one ends of Y switches Y1 and Y2 to bit linesBL1 and BL2 on a sense amplifier 25 side; and clocked inverters 24 and24′ which have inputs and outputs mutually connected, and activation anddeactivation of which are controlled by the sense latch signal LAT. Theinput and output of the clocked inverter 24 the output and input of theclocked inverter 24′) are connected respectively to the bit lines BL1and BL2 of the sense amplifier 25 side. A connection node of the inputof the clocked inverter 24 and the output of the clocked inverter 24′ isconnected to a sense amplifier output SAOUT via an n-channel MOStransistor (pass transistor) that is on-off controlled by a sense latchsignal LAT.

A reference C2 constitutes a True/Bar relationship with the select cellC1, and is composed by a reference cell that is set to a fixedthreshold, a reference transistor, or the like. In the example of FIG.5, a reference is composed by the reference cell C2.

FIG. 6 is a timing waveform diagram showing an operation when READ isperformed, with regard to FIG. 5. In FIG. 6, voltage waveforms of eachof a chip enable signal CE, an output enable signal OE, an addresssignal ADD, a precharge signal PRE, a sensing signal SEN, a sense latchsignal LAT, a word line/Y switch, and a bit line BL when the select cellis on and when the select cell is off, are shown.

The chip enable signal CE and the output enable signal OE are activated(both are activated at a Low level) and are supplied to the peripheralcircuit 30 together with an external address signal ADD, via aninput/output interface 40.

The peripheral circuit part 30 recognizes a READ mode, from values ofthe chip enable signal CE and the output enable signal OE, and sendsaddress information and the sense amplifier activation signal (not shownin FIG. 3) to the memory block 20 at a preset timing.

A word line WL of the select cell C1 and the reference C2, and Yselectors Y1 and Y2 are selected by the decoder circuit 22, and the wordline WL and the Y selectors rise to a High level. At almost the sametiming, the peripheral circuit 30 activates the sensing signal SEN andthe precharge signal PRE, and precharging to a High potential of the bitlines BL1 and BL2 is started.

Next, the precharge signal PRE becomes inactive (Low), and thetransistors M1 and M2 of the precharge circuit are in an off state. Whenthe precharging of the bit lines BL1 and BL2 is completed, the bit lineBL2 of the reference cell C2 is discharged to a GND potential side at aconstant rate.

When the select cell C1 is an on cell (current path between the bit lineand GND is on), the bit line BL1 of the select cell C1 (solid line ofselect cell: on cell in FIG. 6) is discharged to a GND side faster thanthe bit line BL2 of the reference cell C2 (broken line of select cell:on cell in FIG. 6).

When the select cell C1 is an on cell, the bit line BL1 of the selectcell C1 (solid line of select cell: off cell in FIG. 6) is discharged toa GND side slower than the bit line BL2 of the reference cell C2 (brokenline of select cell: off cell in FIG. 6).

At timing at which a potential difference of the bit lines BL1 and BL2is developed to a certain extent (for example, 20 mV to 50 mV), thelatch signal LAT is activated, and an output signal (output of theinverter 24′) from a flip-flop including the inverters 24 and 24′ isoutputted as SAOUT. At a time point of transition of the latch signalLAT from Low to High, the sensing signal SEN is made inactive (Low), theswitches S1 and S2 are set in an off state, and the bit lines BL1 andBL2 of the sense amplifier 25 side are cut off from a bit line on amemory array side. As a result, a cell-directed leakage path is nolonger present. At this time, the word line WL and the Y selectors areboth inactive.

When the latch signal LAT is active (a High pulse period of LAT in FIG.6), the sense amplifier 25, in a state cut off from the bit lines of thememory array side, latches the bit lines BL1 and BL2 to performdifferential output (one of the bit lines BL1 and BL2 is High, and theother is Low). In case that the cell C1 connected to the bit line B11 isan on cell, a value 0 is outputted to SAOUT, when the latch signal LATis active. In case that the cell C1 is an off cell, a value 1 isoutputted to SAOUT, when the latch signal LAT is active.

When the latch signal LAT goes from an active state (High) to aninactive state (Low), a sensing operation in the sense amplifier 25 iscompleted, and SAOUT maintains a latched state (refer to circle mark ofBL in FIG. 6). When the latch signal LAT is inactive and the passtransistor 23 is off, data read the previous time is held in SAOUT, andwhen the latch signal LAT is active and the pass transistor 23 is on,data read this time is delivered to SAOUT. SAOUT is output as DATAoutside a chip via a peripheral circuit PERI and an input/outputinterface.

FIG. 7 is a waveform diagram for describing a READ operation of thememory block 20 in which the regulator described with reference to FIG.1 is used in the regulator unit 10 of FIG. 4. FIG. 7 shows timingoperation of waveforms shown in FIG. 6 (CE, OE, ADD, PRE, SEN, LAT, andSAOUT) and waveforms of FIG. 2 (I1, IN1, IN2, and Vout1).

The sensing signal SEN and the precharge signal PRE are set to High bythe peripheral circuit 30, and in the memory block 20, when theprecharging of the bit lines BL1 and BL2 is started, the output loadcurrent of the regulator unit (REG1) 10 increases. In the presentexemplary embodiment, when the sensing signal SEN and the prechargesignal PRE become High, the first driver control signal IN1 is set toHigh, and potential of the gate node N1 of the drive transistor Q10 ispulled down to a GND potential side, and current supply capability tothe load of the drive transistor Q10 is raised, by the co-operation ofthe n-channel MOS transistors Q8 and Q11 of FIG. 1. When the sensingsignal SEN becomes inactive (Low), the second driver control signal IN2is set to Low, and potential of the gate node N1 of the drive transistorQ10 is pulled up to the power supply voltage VDD side, and currentsupply capability to the load of the drive transistor Q10 is lowered bythe cooperation of the p-channel MOS transistors Q6 and Q13 of FIG. 1,and the output voltage Vout1 decreases and approaches the referencevoltage Vref. In FIG. 7, the output voltage Vout1 indicated by the“related art” is the output voltage of related art of FIG. 10, responseto increase of the load current I1 is slow. After the output voltagerises due to current supply increase of the drive transistor Q10 at thetime of the increase of the load current I1, time until the outputvoltage falls to the reference voltage is also slow.

In FIG. 7, the first driver control signal IN1 rises to High at timingof increasing of the precharge signal PRE to High, and is set to Lowbefore falling of the precharge signal PRE to Low, and an active periodof the first driver control signal IN1 (a High period) is an optionaltime from starting the precharging. Since forced driving does not occur,only a little overdrive due to unnecessary excess supply is needed.

When the precharging is completed, the load current is no longerpresent. In order to promptly transition the current supply capabilityof the regulator to an equilibrium state, it is necessary to shift thenode N1 to the power supply potential VDD side. Accordingly, thep-channel MOS transistor Q14 is turned on, by the second driver controlsignal IN2, the total driver size of the output portion of thedifferential amplifier is increased from the p-channel MOS transistor Q6to that of the p-channel MOS transistors Q6 plus Q13, and the node N1transitions easily to the VDD side. At this time, there is no currentdissipation from the n-channel MOS transistor Q12.

The active period (High period) of the second driver control signal IN2starts with start of a sense latch operation (rising edge of the latchsignal LAT) or end of precharge (falling edge of the precharge signalPRE; refer to broken line for IN2 in FIG. 7), as a trigger, and thistime period is arbitrary. Since forced driving does not occur, there isno Vout2 drop due to an unnecessarily small supply.

FIG. 8 is a diagram showing another configuration example of the memoryblock 20 of FIG. 4. In FIG. 5, a configuration was shown of an EEPROMcell such as a Flash cell or the like. The memory block 20′ of FIG. 8includes a DRAM (Dynamic random Access Memory) cell that requires arefresh operation for data retention. In the memory block 20′ a decodercircuit 27 decodes a row address and activates a selected word line WL.

The sense amplifier includes n-channel MOS transistors N11 and N12connected in series between the bit line pair BLT and BLB, and thep-channel MOS transistors P11 and P12 connected in series between thebit line pair BLT and BLB. The gate of the n-channel MOS transistor N11and the gate of the p-channel MOS transistor P11 are connected in commonto the bit line BLB, and the gate of the n-channel MOS transistor N12and the gate of the p-channel MOS transistor P12 are connected in commonto the bit line BLT. The n-channel MOS transistor N13 that receives thesense signal SEN from the timing circuit 21 at a gate thereof isconnected between GND and a connection node of the n-channel MOStransistors N11 and N12.

The p-channel MOS transistor P13 that receives a sense signal SEP fromthe timing circuit 26 at a gate thereof, is connected between a powersupply VDL and a connection node of the p-channel MOS transistors P11and P12. The sense signals SAP and SEN are supplied to the senseamplifier circuit (N11, N12, P11, P12) in order to develop a potentialdifference between the bit lines BLT and BLB after cell selection. Thatis, when SAP is High and SEN is Low, the sense amplifier circuit (N11,N12, P11, P12) operates. When the voltage of the True bit line BLT ishigher than a logic threshold and the voltage of the Bar bit line BLB islower than the logic threshold, the transistors P11 and N12 are turnedon (the transistors P12 and N11 are off), and BLT and BLB are setrespectively to VDL and GND potentials by the transistors P13 and N13.When the voltage of the True bit line BLT is lower than a logicthreshold and the voltage of the Bar bit line BLB is higher than thelogic threshold, the transistors P12 and N11 are on (the transistors P11and N12 are off), and BLT and BLB are set respectively to GND and VDLpotentials by the transistors N13 and P13.

The p-channel MOS transistors P1 and P2 that receive the prechargesignal PRE from the timing circuit 26 at gates thereof, are connected inseries between the bit line pair BLT and BLB. VBL is connected to aconnection node of the p-channel MOS transistors P1 and P2. When theprecharge signal PRE is at a Low level, p-channel MOS transistors P1 andP2 are turned on and the bit lines BLT and BLB are precharged to avoltage VBL (for example, a voltage-half that of VDL). The p-channel MOStransistor P3 connected between the bit pair BLT and BLB is on when theprecharge signal PRE has a Low level. The p-channel MOS transistor P3 isan equalizer for equalizing the bit line pair BLT and BLB.

A YSW (Y switch) circuit 28 decodes a column address and turns aselected Y switch on.

A read amplifier 29 is made active when a read amplifier activationsignal SAE is activated, and amplifies read data received via the Yswitches Y1 and Y2. A YSW signal output from the YSW circuit 28 performsselection of a column that is output to SAOUT of the read amplifier 29.In the memory block 20′, a plurality of bit line pairs shown in FIG. 8are provided. Each of the bit line pairs is connected to the readamplifier 29 via each of Y switches, and one bit line pair selected bythe YSW circuit 28 is connected to the read amplifier 29.

FIG. 9 is a timing waveform diagram showing an operation when READ isperformed in a circuit of FIG. 8. In FIG. 9, voltage waveforms ofprecharge signal PRE, SAP/SAN, YSW, SAE, word line, BLT and BLB, andSAOUT are respectively shown.

When the precharge (equalize) signal PRE generated by the timing circuit26 is in an active state (Low), the bit line pair BLT and BLB areprecharged to a VBL potential (½ of VDL) and equalized.

When an indicated address is selected, the precharge (equalize) signalPRE is in an inactive state (High), and precharging and equalizing arestopped. At the same time, the selected word line WL is activated, andthe cell transistors C1 and C2 are selected.

When the potential of the word line WL exceeds a threshold of a selectcell, C1 transitions towards a higher level than a VBL level, and C2transitions towards a lower level than the VBL level, according to cellcapacity.

The bit line pair BLT and BLB are amplified respectively to a powersupply potential VDL and GND (ground) potential, by sense signals SAPand SAN. Data selected by YSW is latched by the read amplifier 29, andas SAOUT via the peripheral circuit (30 in FIG. 4) and an input/outputinterface (40 in FIG. 4) is output as read data to outside the chip.

The regulator according to the present invention is preferably used as aregulator for the memory block of FIG. 8. That is, when access to thememory block is started, the load current flows at an operating timingof the circuit, such as a precharge operation or the like, and outputvoltage drops. In order to promptly restore the output voltage drop toan expected value, it is necessary to shift the gate potential N1 of thedrive transistor Q10 of FIG. 1 to a GND (ground) side, and to promptlyincrease current supply capability of the regulator. According to thepresent exemplary embodiment, the n-channel MOS transistor Q12 is turnedon by the control signal IN1, thereby increasing the total driver sizeof the output portion of the differential amplifier from the n-channelMOS transistor Q8 to that of Q8 plus Q11 (in FIG. 3, increasing from then-channel MOS transistor Q1 to Q1 plus Q11). By facilitating transitionof the gate node N1 of the drive transistor Q10 to a GND side, the drivecapability of the regulator is promptly increased. At this time, thereis no current supply from the p-channel MOS transistor Q13. In anactivation period (a High period) of the first driver control signalIN1, pulse adjustment is performed from activation of the sense signalsSEP and SEN lasting for an optional time period. Since forced drivingdoes not occur, only a little overdrive due to unnecessary excess supplyis needed.

When the precharging is completed, the load current is no longerpresent. In order to promptly transition the supply capability of theregulator to an equilibrium state, it is necessary to shift the node N1to the power supply potential VDD side. Accordingly, the p-channel MOStransistor Q14 of FIG. 1 is turned on, by the second driver controlsignal IN2, the total driver size of the output portion of thedifferential amplifier is increased from the p-channel MOS transistor Q6to that of the p-channel MOS transistors Q6 plus Q13 (however, in FIG.3, there is an increase from the p-channel MOS transistor Q3 to that ofQ3 plus Q13), and the node N1 transitions easily to the VDD side. Atthis time, there is no current dissipation from the n-channel MOStransistor Q12. In an activation period (a High period) of the seconddriver control signal IN2, pulse adjustment is performed from the startof activation of the read amplifier 29 or inactivation of the firstdriver control signal IN1, as a trigger, lasting for an optional timeperiod. Since forced driving does not occur, there is no Vout2 drop dueto an unnecessarily small supply.

According to the present invention, even in a case where the loadcurrent of the regulator output has increased, by suppressing variationof the regulator output voltage, it is possible to decrease variation incircuit operation and have high speed access.

In the various abovementioned exemplary embodiments, a DRAM cell orEEPROM cell, such as a FLASH cell and so forth, have been used asexamples. ROM, SRAM (Static Random Access Memory) and so forth are alsopossible.

Within the bounds of the full disclosure of the present invention(inclusive of the scope of the claims), it is possible to modify andadjust the modes and exemplary embodiments of the invention based uponthe fundamental technical idea of the invention. Multifariouscombinations and selections of the various disclosed elements arepossible within the bounds of the scope of the claims of the presentinvention. That is, it goes without saying that the invention coversvarious modifications and changes that would be obvious to those skilledin the art within the scope of the claims.

It should be noted that other objects, features and aspects of thepresent invention will become apparent in the entire disclosure and thatmodifications may be done without departing the gist and scope of thepresent invention as disclosed herein and claimed as appended herewith.Also it should be noted that any combination of the disclosed and/orclaimed elements, matters and/or items may fall under the modificationsaforementioned.

1. A regulator comprising; a differential amplifier including a differential input stage that differentially receives a reference voltage and an output terminal voltage of the regulator; a drive transistor that has an output connected to an output terminal of the regulator and that has a control terminal connected to an output of the differential amplifier; a first transistor connected between the control terminal of the drive transistor and a first power supply terminal; and a second transistor connected between the control terminal of the drive transistor and a second power supply terminal, wherein a control terminal of the first transistor and a control terminal of the second transistor are connected to a first control signal and a second control signal, respectively, the first transistor being on-off controlled by the first control signal and the second transistor being on-off controlled by the second control signal.
 2. A semiconductor device comprising: a regulator as set forth in claim 1; and a memory block including: a precharge circuit that performs precharging of a bit line; and a sense amplifier that is connected to the bit line, the regulator supplying a power supply voltage to the memory block, wherein the first control signal is activated to turn on the first transistor, in response to a start of the precharging of the bit line, and the second control signal is activated to turn on the second transistor, in response to a start of latching of a sensed value by the sense amplifier.
 3. The regulator according to claim 1, wherein the first and second control signals are controlled so as not to be set active simultaneously.
 4. The semiconductor device according to claim 2, wherein the first and second control signals are controlled so as not to be set active simultaneously.
 5. The semiconductor device according to claim 2, wherein the memory block comprises a flash memory.
 6. The semiconductor device according to claim 2, wherein the memory block comprises a dynamic random access memory. 